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ADVANCE INFORMATION
CY62127DV18 MoBL2(R)
1M (64K x 16) Static RAM
Features
* Very high speed: 55 ns * Voltage range: 1.65V to 1.95V * Ultra-low active power -- Typical active current: 0.5 mA @ f = 1 MHz -- Typical active current: 2.5 mA @ f = fMAX * Ultra-low standby power * Easy memory expansion with CE1, CE2 and OE features * Automatic power-down when deselected * CMOS for optimum speed/power * Packages offered in a 48-ball FBGA and a 44-pin TSOP Type II BLE are HIGH. The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected Chip Enable 1 (CE1) HIGH or Chip Enable 2 (CE2) LOW, outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH) or during a write operation (Chip Enable 1 (CE1) LOW and Chip Enable 2 (CE2) HIGH and WE LOW). Writing to the device is accomplished by taking Chip Enable 1 (CE1) LOW and Chip Enable 2 (CE2) HIGH and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A15). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A15). Reading from the device is accomplished by taking Chip Enable 1 (CE1) LOW and Chip Enable 2 (CE2) HIGH and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of read and write modes.
Functional Description[1]
The CY62127DV18 is a high-performance CMOS static RAM organized as 64K words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life (MoBL(R)) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption by 99% when addresses are not toggling. The device can be put into standby mode reducing power consumption by more than 99% when deselected Chip Enable 1 (CE1) HIGH or Chip Enable 2 (CE2) LOW or both BHE and
Logic Block Diagram
DATA IN DRIVERS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
ROW DECODER
64K x 16 RAM ARRAY 2048 x 32 x 16
SENSE AMPS
I/O0 -I/O7 I/O8 -I/O15
COLUMN DECODER
A14
A12
A11
A13
A15
BHE WE OE BLE
CE2 CE1
Power-down Circuit
BHE BLE
CE2 CE1
Note: 1. For best-practice recommendations, please refer to the Cypress application note "System Design Guidelines" on http://www.cypress.com.
Cypress Semiconductor Corporation Document #: 38-05226 Rev. **
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 Revised September 24, 2002
ADVANCE INFORMATION
Pin Configuration[2]
TSOP II (Forward) Top View A4 A3 A2 A1 A0 C1 E I/O1 I/O2 I/O3 I/O4 VCC VSS I/O5 I/O6 I/O7 I/O8 WE A15 A14 A13 A12 NU
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
CY62127DV18 MoBL2(R)
1 BLE I/O 8 I/ 9 O VS S V CC I/ 14 O
FBGA (Top View) 2 3 4 5 OE B HE I/O 10 A0 A3 A5 A1 A4 A6 A7 A2 CE 1 I/O 1 I/O 3 I/O 4 I/O 5 WE A11
6 CE 2 I/O 0 I/O 2 VCC VS S I/O 6 I/ 7 O DNU A B C D E F G H
A5 A6 A7 OE BH E BLE I/O16 I/O15 I/O14 I/O13 VSS VCC I/O12 I/O11 I/O10 I/O9 CE2 A8 A9 A10 A11 DNU
I/O DNU 11
I/O DNU DNU 12 I/O 13 A14 A 12 A9 A15 A13 A10
I/O DNU 15 DNU A8
Note: 2. DNU pins are to be connected to VSS or left open.
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ADVANCE INFORMATION
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage to Ground Potential .........................................................-0.2V to VCCMAX + 0.2V DC Voltage Applied to Outputs in High-Z State[3] ....................................-0.2V to VCC + 0.2V
CY62127DV18 MoBL2(R)
DC Input Voltage[3] ................................ -0.2V to VCC + 0.2V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current .................................................... > 200 mA
Operating Range
Range Industrial Ambient Temperature (TA) -40C to +85C VCC 1.65V to 1.95V
Product Portfolio
Power Dissipation Operating, Icc (mA) VCC Range(V) Product CY62127DV18L CY62127DV18LL Min. 1.65 Typ.
[4]
Max. 1.95
Speed (ns) 55 55
f = 1 MHz Typ.
[4]
f = fMAX Typ.
[4]
Standby, ISB2 (A) Typ.[4] 0.5 0.5 Max. 3 2 5 5
Max. 1
Max.
1.8
0.5
2.5 2.5
Notes: 3. VIL(min.) = -2.0V for pulse durations less than 20 ns. 4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25C.
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ADVANCE INFORMATION
DC Electrical Characteristics (Over the Operating Range)
CY62127DV18 MoBL2(R)
CY62127DV18-55 Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current GND < VI < VCC GND < VO < VCC, Output Disabled Vcc = 1.95V, IOUT = 0mA, CMOS level L LL L LL Test Conditions IOH = -0.1 mA IOL = 0.1 mA VCC = 1.65V VCC = 1.65V 1.4 -0.2 -1 -1 2.5 0.5 0.5 0.5 0.5 0.5 Min. 1.4 0.2 VCC + 0.2 0.4 +1 +1 5 1 3 2 3 2 A A Typ.[4] Max. Unit V V V V A A mA
VCC Operating Supply Cur- f = fMAX = 1/tRC rent f = 1 MHz Automatic CE Power-down Current - CMOS Inputs
ISB1
CE1 > VCC - 0.2V, CE2 < 0.2V, VIN > VCC - 0.2V, VIN < 0.2V, f = fMAX (Address and Data Only), f = 0 (OE, WE, BHE and BLE) CE1 > VCC - 0.2V, CE2 < 0.2V, VIN > VCC - 0.2V or VIN < 0.2V, f = 0, VCC=1.95V
ISB2
Automatic CE Power-down Current - CMOS Inputs
Capacitance [5]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz VCC = VCC(typ) Max. 6 8 Unit pF pF
Thermal Resistance
Parameter JA JC Description Thermal Resistance (Junction to Ambient)[5] Thermal Resistance (Junction to Case)[5] Test Conditions Still Air, soldered on a 3 x 4.5 inch, two-layer printed circuit board BGA 55 16 Unit C/W C/W
Note: 5. Tested initially and after any design or proces changes that may affect these parameters.
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ADVANCE INFORMATION
AC Test Loads and Waveforms
R1 VCC UTPUT GND CL = 30 pF INCLUDING JIG AND SCOPE Equivalent to: OUTPUT R2 Rise Time: 1 V/ns VCC Typ 10% ALL INPUT PULSES 90%
CY62127DV18 MoBL2(R)
90% 10%
Fall Time: 1 V/ns
THEVENIN EQUIVALENT
RTH
V
Parameters R1 R2 R TH VT H
1.8V 1350 0 1080 0 6000 0.80
UNIT V
Data Retention Characteristics
Parameter VDR ICCDR tCDR[5] tR[6] Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time VCC = 1V, CE1 > VCC - 0.2V, CE2 < 0.2V, VIN > VCC - 0.2V or VIN < 0.2V L LL 0 tRC Conditions Min. 1 Typ.[4] Max. 1.95 1 TBD ns ns Unit V A
Data Retention Waveform[7]
DATA RETENTION MODE VDR > 1.0V
VCC CE1 or BHE . BLE or CE2
VCC(min.) tCDR
VCC(min.) tR
Notes: 6. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 100 s or stable at VCC(min.) > 100 s. . 7. BHE BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
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ADVANCE INFORMATION
Switching Characteristics (Over the Operating Range)[8]
CY62127DV18-55 Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE[10] tHZBE Write tWC tSCE tAW tHA tSA tPWE tBW tSD tHD tHZWE tLZWE
Notes:
CY62127DV18 MoBL2(R)
Description Read Cycle Time Address to Data Valid Data Hold from Address Change CE1 LOW or CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to Low-Z[9] OE HIGH to High-Z[9,11] CE1 LOW or CE2 HIGH to Low-Z
[9]
Min. 55
Max.
Unit ns
55 10 55 25 5 20 10 20 0 55 55 5 20 55 45 45 0 0 40 45 25 0 20 10
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
CE1 HIGH or CE2 LOW to High-Z[9,11] CE1 LOW or CE2 HIGH to Power-up CE1 HIGH or CE2 LOW to Power-down BLE/BHE LOW to Data Valid BLE/BHE LOW to Low-Z[9] BLE/BHE HIGH to High-Z[9,11] Cycle[12] Write Cycle Time CE1 LOW or CE2 HIGH to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width BLE/BHE LOW to Write End Data Set-up to Write End Data Hold from Write End WE LOW to High-Z[9,11] WE HIGH to Low-Z[9]
8. Test conditions assume signal transition time of 3 ns or less, timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH and 30-pF load capacitance. 9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 10. If both byte enables are toggled together, this value is 10 ns. 11. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state. 12. The internal Write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE and/or BLE = VIL, CE2 = VIH. All signals must be ACTIVE to initiate a Write and any of these signals can terminate a Write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the Write.
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ADVANCE INFORMATION
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)[13, 14]
tRC ADDRESS tAA tOHA ATA OUT PREVIOUS DATA VALID
CY62127DV18 MoBL2(R)
DATA VALID
Read Cycle No. 2 (OE Controlled)[14, 15]
ADDRESS t RC
CE 1
t PD t HZCE tACE
CE2
BHE /BLE
t DBE t LZBE
OE
t HZBE
t DOE DATA OUT VCC SUPPLY CURRENT
Notes: 13. Device is continuously selected. OE, CE1 = VIL, BHE and/or BLE = VIL, CE2 = VIH. 14. WE is HIGH for Read cycle. 15. Address valid prior to or coincident with CE1, BHE, BLE transition LOW and CE2 transition HIGH.
t HZOE HIGH IMPEDANCE I CC I SB
tLZOE HIGH IMPEDANCE t LZCE tPU 50%
DATA VALID
50%
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ADVANCE INFORMATION
Switching Waveforms (continued)
Write Cycle No. 1 (WE Controlled) [12, 16, 17, 18]
t WC ADDRESS tSCE CE1 CE2 tAW t SA WE t PWE t HA
CY62127DV18 MoBL2(R)
BHE /BLE
tBW
OE tSD ATA I/O
DON'T CARE
t HD
DATA VALID IN t HZOE
Write Cycle No. 2 (CE1 or CE2 Controlled) [12, 16, 17, 18]
t WC ADDRESS t SCE CE 1
CE 2
t SA
t AW t PWE
t HA
WE
BHE /BLE
t BW
OE t SD DATA I/O
DON'T CARE
t HD
DATA IN VALID t HZOE
Notes: 16. Data I/O is high-impedance if OE = VIH. 17. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state. 18. During the DON'T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.
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ADVANCE INFORMATION
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)[17, 18]
tWC ADDRESS tSCE CE1
CY62127DV18 MoBL2(R)
CE2 tAW tSA WE tSD DATA I/O
DON'T CARE
tHA tPWE
tHD
DATAIN VALID tHZWE tLZWE
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[17]
t WC ADDRESS
CE 1 CE 2 t SCE t AW t BW BHE /BLE t SA WE t PWE t SD DATA I/O
DON'T CARE
t HA
t HD
DATAIN VALID
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ADVANCE INFORMATION
Truth Table
CE 1 H X X L L L L L L L L L CE 2 X L X H H H H H H H H H WE X X X H H H H H H L L L OE X X X L L L H H H X X X BHE X X H L H L L H L L H L BLE X X H L L H H L L L L H Input / Outputs High Z High Z High Z Data Out I/O0- I/O15) ( Data Out I/O0- I/O7); ( High Z (I/O8- I/O15) High Z (I/O0- I/O7); Data Out I/O8- I/O15) ( High Z High Z High Z Data In (I/O0- I/O15) Data In (I/O0- I/O7); High Z (I/O8- I/O15) High Z (I/O0- I/O7); Data In (I/O8- I/O15) Mode
CY62127DV18 MoBL2(R)
Power Standby(I SB ) Standby(I SB ) Standby(I SB ) Active CC) (I Active CC) (I Active CC) (I Active CC) (I Active CC) (I Active CC) (I Active CC) (I Active CC) (I Active CC) (I
Deselect/Power-down Deselect/Power-down Deselect/Power-down Read Read Read Output Disabled Output Disabled Output Disabled Write Write Write
Ordering Information
Speed (ns) 55 Ordering Code CY62127DV18L-55BVI CY62127DV18LL-55BVI CY62127DV18L-55ZI CY62127DV18LL-55ZI Package Name BV48A BV48A Z44 Z44 Package Type 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) 44-lead TSOP Type II 44-lead TSOP Type II Operating Range Industrial
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ADVANCE INFORMATION
Package Diagrams
48-ball VFBGA (6 x 8 x 1 mm) BV48A
CY62127DV18 MoBL2(R)
51-85150-*A
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ADVANCE INFORMATION
CY62127DV18 MoBL2(R)
44-pin TSOP II Z44
51-85087-A
MoBL is a registered trademark, and MoBL2 and More Battery Life are trademarks of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05226 Rev. **
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(c) Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
ADVANCE INFORMATION
Document History Page
Document Title: CY62127DV18 MoBL2(R) 1M (64K x 16) Static RAM Document Number: 38-05226 REV. ** ECN NO. 118006 Issue Date 10/01/02 Orig. of Change CDY New Data Sheet
CY62127DV18 MoBL2(R)
Description of Change
Document #: 38-05226 Rev. **
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